Wiring board, semiconductor device, and method of manufacturing wiring board

ABSTRACT

A wiring board includes: a first insulating layer; a first pad region provided above the first insulating layer and having a first connection pad; a second insulating layer provided above the first connection pad and having a first opening to expose the first connection pad; a second pad region provided above the second insulating layer and having a second connection pad electrically connected to the first connection pad; and a third insulating layer provided above the second connection pad, and having a second opening to exposes the first and second connection pads. The first connection pad region is smaller than the second connection pad region.

CROSS-REFERENCE TO RELATED APPLICATION

This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2022-038193, filed on Mar. 11, 2022; the entire contents of which are incorporated herein by reference.

FIELD

Embodiments described herein relate to a wiring board and a semiconductor device.

BACKGROUND

In recent years, the development of communication technology and information processing technology requires miniaturization and high speed of semiconductor devices. To meet this demand, a semiconductor package having a three-dimensional structure of stacked semiconductor chips has been developed.

An example of the semiconductor package has a film-on-device (FOD) structure formed by mounting a chip component onto a printed wiring board and connecting a connection pad of the printed wiring board to the chip component.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic top view illustrating a structure example of a wiring board 1.

FIG. 2 is a schematic cross-sectional view illustrating a structure example of the wiring board 1.

FIG. 3A is a schematic cross-sectional view illustrating a structure example of the wiring board 1.

FIG. 3B is a schematic cross-sectional view illustrating the structure example of the wiring board 1.

FIG. 4 is a schematic view for explaining a size of a chip component.

FIG. 5 is a schematic top view illustrating a structure example of a semiconductor device 100A.

FIG. 6 is a schematic cross-sectional view illustrating the structure example of the semiconductor device 100A.

FIG. 7 is a schematic cross-sectional view illustrating the structure example of the semiconductor device 100A.

FIG. 8 is a schematic top view illustrating a structure example of a semiconductor device 100B.

FIG. 9 is a schematic cross-sectional view illustrating the structure example of the semiconductor device 100B.

FIG. 10 is a schematic cross-sectional view illustrating the structure example of the semiconductor device 100B.

FIG. 11 is a schematic top view illustrating a structure example of the wiring board 1.

FIG. 12 is a schematic cross-sectional view illustrating a structure example of the wiring board 1.

FIG. 13 is a schematic cross-sectional view illustrating a structure example of the wiring board 1.

FIG. 14 is a schematic top view illustrating a structure example of the wiring board 1 in a preparation step.

FIG. 15 is a schematic cross-sectional view illustrating the structure example of the wiring board 1.

FIG. 16 is a schematic cross-sectional view illustrating the structure example of the wiring board 1.

FIG. 17 is a schematic top view illustrating a structure example of the wiring board 1 in an opening step.

FIG. 18 is a schematic cross-sectional view illustrating the structure example of the wiring board 1.

FIG. 19 is a schematic cross-sectional view illustrating the structure example of the wiring board 1.

FIG. 20 is a schematic cross-sectional view illustrating the structure example of the semiconductor device 100A.

FIG. 21 is a schematic cross-sectional view illustrating the structure example of the semiconductor device 100A.

FIG. 22 is a schematic top view illustrating the structure example of the semiconductor device 100B.

FIG. 23 is a schematic cross-sectional view illustrating the structure example of the semiconductor device 100B.

FIG. 24 is a schematic cross-sectional view in the Z-axis direction for explaining a modified method example of manufacturing the wiring board 1.

FIG. 25 is a schematic cross-sectional view in the Z-axis direction for explaining the modified method example of manufacturing the wiring board 1.

DETAILED DESCRIPTION

A wiring board in an embodiment includes: a first insulating layer; a first pad region provided above the first insulating layer and having a first connection pad; a second insulating layer provided above the first connection pad, and having a first opening to expose the first connection pad; a second pad region provided above the second insulating layer and having a second connection pad electrically connected to the first connection pad; and a third insulating layer provided above the second connection pad, and having a second opening to exposes the first and second connection pads. The first connection pad region is smaller than the second connection pad region.

There will be explained an embodiment below with reference to the drawings. The relation between the thickness and the planer dimension of each constituent element, a thickness ratio among the constituent elements, and so on illustrated in the drawings may be different from actual ones. Further, in the embodiment, substantially the same constituent elements are denoted by the same reference numerals and symbols, and explanation thereof will be appropriately omitted.

(Structure Example of a Wiring Board)

A structure example of a wiring board in an embodiment is explained with reference to FIG. 1 , FIG. 2 , and FIG. 3A. FIG. 1 is a schematic top view illustrating a structure example of a wiring board 1, illustrating a portion of the X-Y plane having the X-axis and the Y-axis orthogonal to the X-axis of a chip mounting surface of the wiring board 1. The Z-axis vertical to the chip mounting surface extends along a stacking direction (thickness direction). FIG. 2 is a schematic cross-sectional view illustrating a structure example of the wiring board 1, illustrating an example of a cross section of the wiring board 1 taken along the line segment A1-B1 along the Y-axis direction of the chip mounting surface in FIG. 1 . FIG. 3A is a schematic cross-sectional view illustrating a structure example of the wiring board 1, illustrating an example of a cross section of the wiring board 1 taken along the line segment A2-B2 along the X-axis direction of the chip mounting surface in FIG. 1 . The structure examples of the wiring board in FIG. 1 , FIG. 2 , and FIG. 3A are one example, and the structure example of the wiring board in the embodiment is not limited to these structure examples.

Examples of the wiring board 1 includes a printed wiring board. The wiring board 1 includes an insulating layer 10, a plurality of connection pads 11, an insulating layer 12, a plurality of connection pads 13, a plurality of connection parts 14, and an insulating layer 15. A plurality of internal wiring layers may be formed inside the wiring board 1.

Examples of the insulating layer 10 include a prepreg. The prepreg is a sheet type material such as a glass cloth in which resin is immersed, for example. The insulating layer 10 is not limited to the prepreg, and examples of the insulating layer 10 may include a glass substrate, a ceramic substrate, and a resin substrate such as glass epoxy substrate. In this case, the substrate may be flexible. FIG. 2 and FIG. 3A partially illustrates the insulating layer 10 for convenience.

The connection pads 11 are provided above the insulating layer 10 in the Z-axis direction, for example. The connection pads 11 are provided on the insulating layer 10, for example. The connection pads 11 include a connection pad 11 a and a connection pad 11 b. The number of connection pads 11 is not limited to two (11 a, 11 b) as illustrated in FIG. 1 , and may be three or more.

The connection pads 11 a is apart from the connection pad 11 b and the both connection pads 11 a and 11 b (hereinafter sometimes called just “connection pads 11”) are arranged in the Y-axis direction of an upper surface (the chip mounting surface) of the wiring board 1, for example. The connection pads 11 are provided for mounting a chip component 21, for example. The two-dot chain line in FIG. 2 is an imaginary line, and the region surrounded by the two-dot chain line defines the region of the chip component 21 when the chip component 21 is mounted. The connection pads 11 are formed by using a metal material such as copper, for example.

The insulating layer 12 is provided above the connection pads 11 so as to overlap a portion of each of the connection pads 11 from the insulating layer 10 in the Z-axis direction, for example. The insulating layer 12 has an opening H1 that exposes another portion of each of the connection pads 11. That is, at least a portion of each of the connection pads 11 is exposed from the insulating layer 12. The opening H1 is formed by partially removing the insulating layer 12, for example. Examples of the insulating layer 12 include a prepreg, as similar to the insulating layer 10.

The connection pads 13 are provided above the insulating layer 12 in the Z-axis direction, for example. The connection pads 13 are provided on the insulating layer 12, for example. The connection pads 13 are electrically connected to the connection pads 11 via the connection parts 14, for example. The connection pads 13 include a connection pad 13 a and a connection pad 13 b. The connection parts 14 include a connection part 14 a and a connection part 14 b. The connection pad 13 a is electrically connected to the connection pad 11 a via the connection part 14 a. The connection pad 13 b is electrically connected to the connection pad 11 b via the connection part 14 b. The number of connection pads 13 is not limited to two (13 a, 13 b) as illustrated in FIG. 1 , and may possibly be three or more.

The connection pad 13 a is apart from the connection pad 13 a and the both connection pads 13 a and 13 b (hereinafter sometimes called just “connection pads 13”) are arranged in the X-axis direction of the chip mounting surface of the wiring board 1, for example. The connection pads 13 are provided for mounting a chip component 22 that is larger in size than the chip component 21, for example. The two-dot chain line in FIG. 3A is an imaginary line, and the region surrounded by the two-dot chain line defines the region of the chip component 22 when the chip component 22 is mounted. The connection pads 13 are formed by using a metal material such as copper, for example. FIG. 3A illustrates an example where the connection pads 13 are formed on the upper surface of the wiring board 1, but the connection pads 13 are not limited to this structure, and the connection pads 13 may be provided in an inner layer of the wiring board 1.

One of the connection parts 14 electrically connects one of the connection pads 11 and one of the connection pads 13. The other of the connection parts 14 electrically connects the other of the connection pads 11 and the other of the connection pads 13. FIG. 1 schematically illustrates the connection part 14 a and the connection part 14 b as the connection parts 14. Examples of the connection parts 14 may include a wiring or a via. That is, the connection part 14 may be formed of a wiring as illustrated in FIG. 1 or may be formed of a via as illustrated in FIG. 3B. FIG. 3B illustrates an example of a cross section of the wiring board 1 taken along the line segment A3-B3 along the X-axis direction of the chip mounting surface in FIG. 1 . The positions of the connection parts 14 are not limited. When the connection parts 14 are formed of vias, the connection parts 14 are formed by using a metal material such as copper, for example.

The insulating layer 15 is provided above the connection pads 13 from the insulating layer 12. The insulating layer 15 is provided on the insulating layer 12, for example. Examples of the insulating layer 15 include a solder resist. The insulating layer 15 has an opening H2 that exposes the connection pads 11 and the connection pads 13. The connection pads 11 and the connection pads 13 only need to be partially exposed from the insulating layer 15. The opening H2 is formed by partially removing the insulating layer 15 for the connection pads being partially exposed, for example.

Examples of the chip component 21 and the chip component 22 include a chip resistor, and a chip capacitor. The chip component 21 and the chip component 22 have the same function as each other. For example, if the chip component 21 is a chip resistor, the chip component 22 is also a chip resistor, and if the chip component 21 is a chip capacitor, the chip component 22 is also a chip capacitor. Either the chip component 21 or the chip component 22 is mounted on the wiring board 1.

The chip component 21 and the chip component 22 have different sizes. The size of these chip components can be expressed by an abbreviation consisting of a four- or five-digit number specified according to the combination of a length L (mm) of the chip component×a width D (mm) of the chip component, for example, by the Japanese Industrial Standards (JIS) or the Electronic Industries Alliance (EIA) standards. FIG. 4 is a three-dimensional schematic view for explaining the size of the chip component. Table 1 illustrates the relationship between a size of a chip component and an abbreviation of a size (L, D). For example, when the chip component 22 is a chip represented by 0603 in JIS abbreviation, the chip component 21 is a chip represented by 0402 in JIS abbreviation. As illustrated, the chip component 22 has a larger size than the chip component 21 in this embodiment.

TABLE 1 Length L Width D JIS abbreviation EIA abbreviation (mm) (mm) (mm notation) (inch notation) 0.4 0.2 0402 01005 0.6 0.3 0603 0201 1.0 0.5 1005 0402 1.6 0.8 1608 0603 2.0 1.25 2012 0805 3.2 1.6 3216 1206 3.2 2.5 3225 1210 5.0 2.5 5025 2010 6.4 3.2 6432 2512

The region surrounded by the two-dot chain line in FIG. 3A where the chip component is mounted includes an area having the connection pads for the chip component (to be also referred to as a pad region, here). That is, the area of the chip component and the area of the pad region are almost equal, if seen from X-Y plane, although the pad region is slightly larger. Therefore, the size of the pad region is designed slightly larger than the size of the chip component to be mounted.

In general, the connection pad is to design totally so as to optimize the wiring board, considering the connection relationship with another chip component, electrical conditions of resistance and capacitance, and other factors. However, even if the connection pad is designed totally as described above, the chip component may be replaced with another chip component due to a change in specifications or other reasons. In this case, if the alternative chip component is the same in size as the chip component, the chip component can be simply replaced with the alternative chip component as is. But if the alternative chip component has a different size, the wiring board needs to be redesigned.

Therefore, the wiring board in this embodiment has a plurality of pad regions having different sizes. This structure can change the size of the chip component to be mounted without manufacturing or preparing a new wiring board even if it needs to change the size of the chip component to be mounted. Therefore, the wiring board according to the embodiment is able to provide a high versatility.

In order to make the size of the chip component to be mounted changeable, it is conceivable to form a plurality of connection pads having different sizes on the same surface of the wiring board. However, if the distance between the neighboring connection pads having different sizes becomes narrow, it becomes difficult to form a conductive layer for each of the connection pads.

In contrast, the wiring board according to the embodiment includes a plurality of the pad regions having different sizes in different layers of the wiring board and therefore the pad regions having different sizes are apart from each other in the Z-axis direction. This structure allows to form a conductive layer for each of the connection pads easily even if the distance between the neighboring connection pads having different sizes becomes narrow, if seen from X-Y plane.

The pad region of the chip component 21 having the connection pads 11 is smaller than that of the chip component 22 having the connection pads 13.

The connection pads 11 a and 11 b are arranged, if seen from X-Y plane, in a direction intersecting the direction of which the connection pads 13 a and 13 b are arranged. Further, the connection pads 11 a and 11 b are arranged between the connection pads 13 a and the connection pad 13 b in the X-axis direction. Either the chip component 21 or the chip component 22 is selectively mounted on the wiring board 1. Thus, such different layered arrangement can reduce the size of the mounting regions for these chip components. As a result, an occupancy area for the chip components 21 and 22 of the wiring board 1 can be reduced and therefore the wiring board 1 itself can be miniaturized rather than the case of forming the connection pads having on the same surface of the wiring board. Further, for example, an amount of the solder resist to be used for the insulating layer 15 can also be reduced. Further, the versatility when selectively mounting the chip component can be improved.

The width of each of the connection pads 11 a and 11 b in the X-axis direction may be smaller than the distance between the connection pads 13 a and 13 b in the X-axis direction. The distance between the connection pads 11 a and 11 b in the Y-axis direction may be smaller than the distance between the connection pads 13 a and 13 b in the X-axis direction.

(Structure Example of a Semiconductor Device)

A structure example of a semiconductor device where the chip component 21 is mounted on the wiring board 1 is explained with reference to FIG. 5 , FIG. 6 , and FIG. 7 . FIG. 5 is a schematic top view illustrating a structure example of a semiconductor device 100A, illustrating a portion of the X-Y plane having the X-axis and the Y-axis of the chip mounting surface of the wiring board 1. FIG. 6 is a schematic cross-sectional view illustrating the structure example of the semiconductor device 100A, taken along the line segment A1-B1 in FIG. 5 . FIG. 7 is a schematic cross-sectional view illustrating the structure example of the semiconductor device 100A, taken along the line segment A2-B2 in FIG. 5 . For each of the parts of the wiring board 1 illustrated in FIG. 5 , FIG. 6 , and FIG. 7 corresponding to the parts of the wiring board 1 illustrated in FIG. 1 , FIG. 2 , and FIG. 3A, an explanation for the parts of the wiring board 1 illustrated in FIG. 1 , FIG. 2 , and FIG. 3A can be appropriately cited if necessary.

When the chip component 21 is mounted on the wiring board 1, the chip component 21 is mounted on the connection pads 11 as illustrated in FIG. 5 , FIG. 6 , and FIG. 7 . In this case, the chip component 21 is provided between the connection pad 13 a and the connection pad 13 b, and is not provided on the connection pads 13 a and 13 b.

A structure example of the semiconductor device where the chip component 22 is mounted on the wiring board 1 is explained with reference to FIG. 8 , FIG. 9 , and FIG. 10 . FIG. 8 is a schematic top view illustrating a structure example of a semiconductor device 100B, if seen from the X-Y plane. FIG. 9 is a schematic cross-sectional view illustrating the structure example of the semiconductor device 100B, taken along the line segment A1-B1 in FIG. 8 . FIG. 10 is a schematic cross-sectional view illustrating the structure example of the semiconductor device 100B, taken along the line segment A2-B2 in FIG. 8 . For each of the parts of the wiring board 1 illustrated in FIG. 8 , FIG. 9 , and FIG. 10 corresponding to the wiring board 1 illustrated in FIG. 1 , FIG. 2 , and FIG. 3A, an explanation for the parts of the wiring board 1 illustrated in FIG. 1 , FIG. 2 , and FIG. 3A can be appropriately cited if necessary.

When the chip component 22 is mounted on the wiring board 1, the chip component 22 is mounted on the connection pads 13 as illustrated in FIG. 8 , FIG. 9 , and FIG. 10 . In this case, the chip component 22 is provided apart from the connection pads 11 a and 11 b in the Z-axis direction, and is not provided on the connection pads 11.

(Modified Example of the Wiring Board)

The wiring board 1 may further include connection pads different from the connection pads 11 and the connection pads 13. A modified example of the wiring board in the embodiment is explained with reference to FIG. 11 , FIG. 12 , and FIG. 13 . FIG. 11 is a schematic top view illustrating another structure example of the wiring board 1, if seen from X-Y plane. FIG. 12 is a schematic cross-sectional view illustrating another structure example of the wiring board 1, taken along the line segment A1-B1 in FIG. 11 . FIG. 13 is a schematic cross-sectional view illustrating another structure example of the wiring board 1, taken along the line segment A2-B2 in FIG. 11 . For each of the parts of the wiring board 1 illustrated in FIG. 11 , FIG. 12 , and FIG. 13 corresponding to the parts of the wiring board 1 illustrated in FIG. 1 , FIG. 2 , and FIG. 3A, an explanation for the parts of the wiring board 1 illustrated in FIG. 1 , FIG. 2 , and FIG. 3A can be appropriately cited if necessary.

The connection pads 11 illustrated in FIG. 11 are provided for mounting a chip component 31, for example. The two-dot chain line in FIG. 12 is an imaginary line. The upper region surrounded by the two-dot chain line defines the region of the chip component 31 when the chip component 31 is mounted. The lower region surrounded by the two-dot chain line defines the region of the chip component 33 when the chip component 33 is mounted.

The connection pads 13 illustrated in FIG. 13 are provided for mounting a chip component 32 that is larger in size than the chip component 31, for example. The two-dot chain line in FIG. 13 is an imaginary line. The upper region surrounded by the two-dot chain line defines the region of the chip component 32 when the chip component 32 is mounted. The lower region surrounded by the two-dot chain line defines the region of the chip component 33 when the chip component 33 is mounted.

The modified example of the wiring board 1 further includes a plurality of connection pads 16 and an insulating layer 17 between the insulating layers 10 and 12. The connection pads 16 includes a connection pad 16 a and a connection pad 16 b.

The connection pads 16 are provided above the insulating layer 10 in the Z-axis direction, for example. The connection pads 16 are provided on the insulating layer 10, for example. The connection pads 16 are electrically connected to the connection pads 11 and the connection pads 13 via the connection parts 14, for example. The connection pad 16 a is electrically connected to the connection pad 11 a and the connection pad 13 a via the connection part 14 a. The connection pad 16 b is electrically connected to the connection pad 11 b and the connection pad 13 b via the connection part 14 b. Examples of the connection parts 14 a and 14 b include a wiring or a via. The number of connection pads 16 is not limited to two (16 a, 16 b) as illustrated in FIG. 11 , and may possibly be three or more.

The connection pads 16 are arranged in the X-axis direction of the chip mounting surface of the wiring board 1, for example. The connection pads 16 are provided for mounting a chip component 33 that is smaller in size than the chip component 31, for example. The connection pads 16 are formed by using a metal material such as copper, for example.

The insulating layer 17 is provided between the insulating layer 10 and the insulating layer 12. The insulating layer 17 is provided so as to overlap a portion of each of the connection pads 16 from the insulating layer 10 in the Z-axis direction, for example. The connection pads 11 are provided above the insulating layer 17. The insulating layer 17 has an opening H0 that exposes the other portion of each of the connection pads 16. That is, at least a portion of each of the connection pads 16 is exposed from the insulating layer 17. The opening H0 is formed by partially removing the insulating layer 17 for the connection pads 16 being partially exposed, for example. Examples of the insulating layer 17 include a prepreg, as similar to the insulating layer 10.

Examples of each of the chip component 31, the chip component 32, and the chip component 33 include a chip resistor, and a chip capacitor. The chip component 31, the chip component 32, and the chip component 33 have the same function as one another. For example, if the chip component 31 and the chip component 32 are a chip resistor, the chip component 33 is also a chip resistor, and if the chip component 31 and the chip component 32 are a chip capacitor, the chip component 33 is also a chip capacitor.

The chip component 31, the chip component 32, and the chip component 33 have different sizes. The size of these chip components can be represented by an abbreviation of JIS or EIA standards similarly to the chip component 21 and the chip component 23. For example, when the chip component 31 is a chip represented by 0603 in JIS abbreviation, the chip component 32 is a chip represented by 1005 in JIS abbreviation and the chip component 33 is a chip represented by 0402 in JIS abbreviation. As illustrated, the chip component 32 has a larger size than the chip components 31 and 33 in this embodiment, and the chip component 33 has a smaller size than the chip components 31 and 32 in this embodiment. Any component of the chip component 31, the chip component 32, and the chip component 33 is mounted on the wiring board 1.

Here, the area of the pad region having the connection pads 16 for the chip component 33 is smaller than the area of the pad region having the connection pads 11 for the chip component 31. This structure can change the size of the chip component to be mounted without manufacturing or preparing a new wiring board even if it needs to change the size of the chip component to be mounted. Therefore, the wiring board according to the embodiment is able to provide a high versatility. This modified example explains one example where three layers of connection pads having different heights in the Z-axis direction are provided, but four or more layers of connection pads may be further provided.

The connection pad 16 a is apart from the connection pad 16 b and the both connection pads 16 a and 16 b (hereinafter sometimes called just “connection pads 16”) are arranged, if seen from X-Y plane, in a direction intersecting the direction of which the connection pads 11 a and 11 b are arranged. Further, the connection pads 16 a and 16 b are provided between the connection pads 11 a and 11 b in the Y-axis direction. When any one of the chip component 31, the chip component 32, and the chip component 33 is selectively mounted on the wiring board 1 and the connection pads 11, 13 and 16 having different sizes are arranged in the Z-axis direction as in the modified example, an occupancy area for the chip component of the wiring board 1 can be reduced rather than the case of forming the connection pads having the different sizes on the same surface of the wiring board 1. Further, for example, an amount of the solder resist to be used for the insulating layer 15 can also be reduced. In addition, the versatility when selectively mounting the chip component can be improved.

The width of each of the connection pads 16 a and 16 b in the Y-axis direction may be smaller than the distance between the connection pads 11 a and 11 b in the Y-axis direction. The distance between the connection pads 16 a and 16 b in the X-axis direction may be smaller than the distance between the connection pads 11 a and 11 b in the Y-axis direction. This can reduce the mounting region of the chip component 33 to reduce the area of the wiring board 1. This modified example is shown as the connection pads 11, the connection pads 13, and the connection pads 16 are connected and any one of the chip components is selectively arranged, the connection parts 14 may be formed so that two of the chip components can be selectively arranged, depending on each size of the selected chip components.

(Method Example of Manufacturing the Wiring Board)

A method example of manufacturing the wiring board, includes a preparation step and an opening step. FIG. 14 is a schematic top view illustrating a structure example of the wiring board 1 in the preparation step, illustrating a portion of the X-Y plane. The Z-axis vertical to the chip mounting surface extends in the stacking direction (the thickness direction of the wiring board 1) of the insulating layers 10 and 12. FIG. 15 is a schematic cross-sectional view illustrating the structure example of the wiring board 1, taken along the line segment A1-B1 in FIG. 14 . FIG. 16 is a schematic cross-sectional view illustrating the structure example of the wiring board 1, taken along the line segment A2-B2 in FIG. 14 . For each of the parts of the wiring board 1 illustrated in FIG. 14 , FIG. 15 , and FIG. 16 corresponding to the parts of the wiring board 1 illustrated in FIG. 1 , FIG. 2 , and FIG. 3A, an explanation for the parts of the wiring board 1 illustrated in FIG. 1 , FIG. 2 , and FIG. 3A can be appropriately cited if necessary.

In the preparation step, a stack 1A having the insulating layer 10, the connection pads 11, the insulating layer 12, a conductive layer 130, and the insulating layer is prepared. The stack 1A may include the connection parts 14 such as vias as illustrated in FIG. 3B.

The conductive layer 130 is provided above the insulating layer 12. The conductive layer 130 extends in the X-axis direction, for example. The conductive layer 130 is provided for forming the connection pads 13.

FIG. 17 is a schematic top view illustrating a structure example of the wiring board 1 in the opening step, illustrating a portion of the X-Y plane. FIG. 18 is a schematic cross-sectional view illustrating the structure example of the wiring board 1, taken along the line segment A1-B1 in FIG. 17 . FIG. 19 is a schematic cross-sectional view illustrating the structure example of the wiring board 1, taken along the line segment A2-B2 in FIG. 17 .

In this opening step, a part of each of the insulating layer 12 and the conductive layer 130 is removed. This step can separate the conductive layer 130 into the connection pad 13 a and the connection pad 13 b and form the opening H1 that exposes at least a portion of each of the connection pads 11 a and 11 b below the connection pads 13 a and 13 b. The insulating layer 12 and the conductive layer 130 can be partially removed by irradiating them with a laser beam, for example. The connection pad 13 a and 13 b is formed, and then the connection parts 14 such as wirings as illustrated in FIG. 3A may be formed.

Using the method through FIG. 17 to FIG. 19 , the wiring board 1 can be manufactured. The method example in the embodiment, includes partially removing the insulating layer 12 and the conductive layer 130 to form the opening H1 that exposes the connection pads 11 a and 11 b. Therefore, even when the distance between the connection pads having different sizes become narrow, if seen from X-Y plane, the connection pads are apart from each other in the Z-axis direction, and thus the method example can easily form the connection pads.

(Method Example of Manufacturing the Semiconductor Device)

A method example of manufacturing the semiconductor device 100A when the chip component 21 is mounted on the wiring board 1 is explained with reference to FIG. and FIG. 21 . FIG. 20 is a schematic cross-sectional view illustrating the structure example of the semiconductor device 100A, taken along the line segment A1-B1 of FIG. 17 . FIG. 21 is a schematic cross-sectional view illustrating the structure example of the semiconductor device 100A, taken along the line segment A2-B2 of FIG. 17 . For each of the parts of the wiring board 1 illustrated in FIG. 20 and FIG. 21 corresponding to the parts of the wiring board 1 illustrated in FIG. 17 , FIG. 18 , and FIG. 19 , an explanation for the parts of the wiring board 1 illustrated in FIG. 17 , FIG. 18 , and FIG. 19 can be appropriately cited if necessary.

When mounting the chip component 21 on the wiring board 1, as illustrated in FIG. 20 and FIG. 21 , solder 30 a is applied onto the surfaces of the connection pads 11, and the connection pads 11 and connection terminals of the chip component 21 are bonded together via the solders 30 a. The solder 30 a is applied by using a jet dispenser, for example. The solder 30 a is formed by using a metal material such as silver, for example.

A method example of manufacturing the semiconductor device 100B when the chip component 22 is mounted on the wiring board 1 is explained with reference to FIG. 22 and FIG. 23 . FIG. 22 is a schematic cross-sectional view illustrating the structure example of the semiconductor device 100B, taken along the line segment A1-B1 of FIG. 17 . FIG. 23 is a schematic cross-sectional view illustrating the structure example of the semiconductor device 100B, taken along the line segment A2-B2 of FIG. 17 . For each of the parts of the wiring board 1 illustrated in FIG. 22 and FIG. 23 corresponding to the parts of the wiring board 1 illustrated in FIG. 17 , FIG. 18 , and FIG. 19 , an explanation for the parts of the wiring board 1 illustrated in FIG. 17 , FIG. 18 , and FIG. 19 can be appropriately cited if necessary.

When mounting the chip component 22 on the wiring board 1, as illustrated in FIG. 22 and FIG. 23 , solder 30 b is applied onto the surfaces of the connection pads 13, and the connection pads 13 and connection terminals of the chip component 22 are bonded together via the solders 30 b. The solder 30 b is applied by using a jet dispenser, for example. The solder 30 b is formed by using a metal material such as silver, for example.

(Modified Method Example of Manufacturing the Wiring Board)

A modified method example of manufacturing the wiring board is explained with reference to FIG. 24 and FIG. 25 . This method example include a step of forming through holes, and a step of forming a conductive layer into the through holes to form a plurality of vias 14. FIG. 24 and FIG. 25 are schematic cross-sectional views in the Z-axis direction illustrating a modified method example of manufacturing one pad portion of the wiring board. For each of the parts of the wiring board illustrated in FIG. 24 and FIG. corresponding to the parts of the wiring board 1 illustrated in FIG. 1 , FIG. 2 , and FIG. 3A, an explanation for the parts of the wiring board 1 illustrated in FIG. 1 , FIG. 2 , and FIG. 3A can be appropriately cited if necessary.

As illustrated in FIG. 24 , the through hole (referred to as TH in the figure) forming step is a step that penetrates a connection pad 11 x, the insulating layer 12, a connection pad 13 x, an insulating layer 18, and a connection pad 19 x, for example, in the Z-axis direction. The through hole forming step may be performed before or after forming the opening H1 (opening forming step).

The connection pad 11 x is one of the connection pads 11.

The connection pad 13 x is one of the connection pads 13.

The insulating layer 18 is provided on the opposite side of the insulating layer from the insulating layer 12, for example. Examples of the insulating layer 18 include a prepreg, as similar to the insulating layer 10. The wiring board 1 may include another insulating layer or a conductive layer that forms an internal wiring between the insulating layer 10 and the insulating layer 18.

The connection pad 19 x is a pad selected from a plurality of connection pads 19. The connection pad 19 x has a function as an external connection terminal, for example. The connection pads 19 are provided above the insulating layer 18 from the insulating layer 10. The connection pads 19 can be formed by using the same material and method as those of the connection pads 13, for example.

The through hole TH can be formed by machining using a drill, for example. The through hole TH is formed, and then a desmear process may be performed.

As illustrated in FIG. 25 , the via forming step includes forming a conductive layer onto an inner wall surface of the through hole TH to form a via 14 x. The conductive layer is formed by, for example, a plating method using a material applicable to the via 14.

The via 14 x is a via selected from the vias 14. The via 14 x connects the connection pad 11 x, the connection pad 13 x, and the connection pad 19 x.

As described above, the modified method example in the embodiment includes forming the via 14 x in the through hole TH, and thus can electrically connects the connection pad 11 x and the connection pad 13 x.

While certain embodiments have been described, the above-described embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions. 

What is claimed is:
 1. A wiring board, comprising: a first insulating layer; a first pad region provided above the first insulating layer and having a first connection pad; a second insulating layer provided above the first connection pad and having a first opening to expose the first connection pad; a second pad region provided above the second insulating layer and having a second connection pad electrically connected to the first connection pad; and a third insulating layer provided above the second connection pad, and having a second opening to exposes the first and second connection pads, wherein the first connection pad region is smaller than the second connection pad region.
 2. The wiring board according to claim 1, further comprising: a plurality of the first connection pads; and a plurality of the second connection pads, wherein the plurality of the first connection pads are arranged in a first direction, the plurality of the second connection pads are arranged in a second direction intersecting the first direction, and the plurality of the first connection pads are arranged between one of the plurality of the second connection pads and another of the plurality of the second connection pads in the second direction.
 3. The wiring board according to claim 2, wherein the width of each of the plurality of the first connection pads in the second direction is smaller than the distance between the plurality of the second connection pads in the second direction, and the distance between the plurality of the first connection pads in the first direction is smaller than the distance between the plurality of the second connection pads in the second direction.
 4. The wiring board according to 1, wherein the first connection pad is provided for mounting a first component, and the second connection pad is provided for mounting a second component larger in size than the first component.
 5. The wiring board according to claim 3, wherein the first component and the second component each are a chip resistor and either one of the chip resistors is mounted on the corresponding connection pad while the other of the chip resistors is not mounted on the other connection pad.
 6. The wiring board according to claim 3, wherein the first component and the second component each are a chip capacitor and either one of the chip capacitors is mounted on the corresponding connection pad while the other of the chip capacitors is not mounted on the other connection pad.
 7. The wiring board according to claim 3, wherein the first component has a length of 0.4 mm or less and a width of 0.2 mm or less, and the second component has a length of 0.6 mm or more and a width of 0.3 mm or more.
 8. A semiconductor device, comprising: a wiring board comprising: a first insulating layer; a first pad region provided above the first insulating layer and having a first connection pad mountable of a first component; a second insulating layer provided above the first connection pad, and having a first opening to expose the first connection pad; a second pad region provided above the second insulating layer and having a second connection pad electrically connected to the first connection pad mountable of a second component, a size of the second component is larger than that of the first component; and a third insulating layer provided above the second connection pad, and having a second opening to expose the first connection pad and the second connection pad, in which the first pad region is smaller than the second pad region, wherein either one of the first component or the second component is selectively mounted on the corresponding connection pad.
 9. The semiconductor device according to claim 8, wherein the wiring board further comprise: a plurality of the first connection pads; and a plurality of the second connection pads, the plurality of the first connection pads are arranged in a first direction, the plurality of the second connection pads are arranged in a second direction intersecting the first direction, and the plurality of the first connection pads are arranged between one of the plurality of the second connection pads and another of the plurality of the second connection pads in the second direction.
 10. The semiconductor device according to claim 9, wherein the width of each of a plurality of the first connection pads in the second direction is smaller than the distance between the plurality of the second connection pads in the second direction, and the distance between the plurality of the first connection pads in the first direction is smaller than the distance between the plurality of the second connection pads in the second direction.
 11. The semiconductor device according to claim 8, wherein the first connection pad is provided for mounting the first component, and the second connection pad is provided for mounting the second component.
 12. The semiconductor device according to claim 11, wherein the first and second components each are a chip resistor.
 13. The semiconductor device according to claim 11, wherein the first and second components each are a chip capacitor.
 14. The semiconductor device according to claim 11, wherein the first component has a length of 0.4 mm or less and a width of 0.2 mm or less, and the second component has a length of 0.6 mm or more and a width of 0.3 mm or more.
 15. A method of manufacturing a wiring board, comprising: preparing a stack, the stack comprising: a first insulating layer; a first pad region provided above the first insulating layer and having a first connection pad; a second insulating layer provided above the first pad region; and a conductive layer provided above the second insulating layer; and partially removing each of the second insulating layer and the conductive layer to form a first opening and a second pad region, the first opening exposing at least a part of the first connection pad, and the second pad region having a second connection pad, wherein the second connection pad is electrically connected to the first connection pad, and the first connection pad region is smaller than the second connection pad region.
 16. The method according to claim 15, wherein the wiring board comprises: a plurality of the first connection pads; and a plurality of the second connection pads, the plurality of the first connection pads are arranged in a first direction, the plurality of the second connection pads are arranged in a second direction intersecting the first direction, and the plurality of the first connection pads are arranged between one of the plurality of the second connection pads and another of the plurality of the second connection pads in the second direction.
 17. The method according to claim 15, wherein the first connection pad is provided for mounting a first component, and the second connection pad is provided for mounting a second component that is larger in size than the first component.
 18. The method according to claim 17, wherein the first and second components each are a chip resistor.
 19. The method according to claim 17, wherein the first and second components each are a chip capacitor.
 20. The method according to claim 17, wherein the first component has a length of 0.4 mm or less and a width of 0.2 mm or less, and the second component has a length of 0.6 mm or more and a width of 0.3 mm or more. 